Engineering
Poster
Nanoscaled devices fabricated by combined nanoimprint- and photolithography (CNP)
Khaled Arzi, Universität Duisburg-Essen, Duisburg, GermanyChristian Blumberg, Universität Duisburg-Essen, Duisburg, GermanyLisa Liborius, Universität Duisburg-Essen, Duisburg, GermanyWerner Prost, Universität Duisburg-Essen, Duisburg, GermanyArtur Poloczek, Universität Duisburg-Essen, Duisburg, GermanyFranz-Josef Tegude, Universität Duisburg-Essen, Duisburg, Germany
Downscaling is still a major approach for further improvement of specific parameters for (opto-)electronic devices. Therefore, the nanoimprint-lithography (NIL) is one of the most promising tools for highly scaled mass production.
Critical feature sizes can be realised using the electron beam lithography (EBL) aligned precisely to existing sample structures. In contrast to this slow and expensive method, NIL offers parallel structure processing down to the nanometer range. Actually, NIL-machines are commercially available as stand-alone tools or as upgrades for optical lithography mask aligners. In any case, they require an appreciable invest of financial resources and might be unattainable for small companies or university research labs.
In this contribution, we present a self-made two inch NIL-tool using the 3D printing technology for hardware production. It offers a highly functional and low-cost solution for research purposes. The feasible structure dimensions range from 15 µm down to 25 nm. Stamped alignment marks are used for the combination with subsequent photolithography layers. Here, the overlay accuracy of NIL-structures with optical masks is still challenging, but an improvement of the distortion by introducing glass carriers for PDMS stamps is possible. Further on, we demonstrate our strategy for the reproduction of PDMS stamps, which suffer from a strong deterioration caused by common usage.
Our motivation for submicron-scaling of InGaAs/AlAs/InAs Resonant Tunnelling Diodes (RTD) is the enhancement of the device towards a Resonant Tunneling Transistor (RTT) where the carrier transport is controlled by a surrounding wrap-gate electrode using the field effect. Physical simulations have shown that mesa diameters of RTTs may not exceed a few 100 nm in order to obtain noticeable carrier control.
With respect to Heterojunction Bipolar Transistors (HBT), scaling of the emitter area generally improves the emitter access resistance, which mainly influences the high frequency performance of the device. “Emitter-regrowth” was one of the improvement strategies in the past. At this point, we propose the definition of the emitter area using NIL.
We present the successful application of our NIL-solution on scaling of the mentioned electronic top-down devices. Therefore, the integration of the critical NIL-structures into the standard process flow using optical lithography will be discussed.